The erase circuit is configured to erase the first memory cell of the first word line for a first duration and erase the second memory cell of the second word line for a second duration, such that the first duration is different than the second duration. The apparatus further comprises an erase circuit coupled to the set of memory cells. The set of memory cells includes a first memory cell coupled to a first word line and a second memory cell coupled to a second word line. The memory channel comprises a first end electrically coupled to a substrate and a second end electrically coupled to a bit line.
One innovative aspect includes an apparatus comprising: a memory block comprising a set of memory cells of a memory channel. SUMMARYĪpparatuses, methods, systems, and/or other aspects are presented for reducing occurrence of grown bad blocks (GBB) during an erase operation. Word-line-memory-hole-shorts do not only cause permanent program failure but also, cumulatively cause storage device failures. This is highly undesirable since this high electric stress usually leads to word-line-memory-hole-shorts (i.e., grown bad blocks). When memory strings having this funnel-like shape are energized during either a program/erase operation associated with memory cells coupled to the memory string, a high electric stress can develop across such memory strings. For example, the etching of memory strings/memory holes/memory channels (to which bit lines and source lines are coupled to) of 3D-NANDs results in a funnel-like shape for each memory string.
This has led to significant increases in memory cell density and more precisely, storage capacity of modern flash storage devices.Įxisting fabrication techniques for building 2D and 3D-NAND storage devices introduce structural and other design limitations that can negatively affect the operation of NAND storage devices. BACKGROUNDĪdvances in the design and fabrication of 2D and 3D-NAND devices have revolutionized flash storage technology by stacking memory cells on top of each other to optimize usage of storage device real estate. The present disclosure pertains generally to operation of memory devices, and more specifically to mitigating grown bad blocks in non-volatile memory devices.